EasyChip
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Fifty production tools,
built by two people

EasyChip Private Limited, Bengaluru. Pre-seed, and building.

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[ Chapter - 04 ]
Why we exist

We met at BITS Pilani Goa doing device-physics research on Cadence and Sentaurus TCAD. The tools were slow enough that the workaround became the company.

India holds roughly a fifth of the world’s chip design engineers and owns none of the tools they design with. Three vendors hold 74% of the market. That is a structural monopoly, not a competitive one.

Team

Two founders who hit this problem before they named it

Co-founder & CEO

Rakshit Mishra

Product and frontend. Owns customer development, industry validation, and every conversation that has put a build in front of a practising engineer.

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Co-founder & CTO

Parth Parekh

Backend, infrastructure and AI systems. Owns the orchestration layer, the delivery pipeline, and the ML layer now being built across the suite.

LinkedIn
IncubationBITS Pilani SMCC WILP - a two-year MoU for co-development and resource sharing toward MVP development. Workspace, stipend and mentors. No equity taken.
₹0Capital raisedThe suite was built without outside capital. That number is the argument.
Deliberately narrowWe do not attempt the core signoff engines, and we say so in every room.
Validation

Forty-one engineers told us the same four things.

Surveys across CAD/EDA and RTL design roles, plus five to six sessions where we put a working build in front of a practising engineer and watched them use it.

01Determinism before featuresIf a rerun is not bit-identical, the result cannot be trusted at signoff. This came back more often than any feature request.
02Licence servers are a daily taxSeat contention, daemon failures and checkout waits cost hours a week. An offline signed licence was described as a reason to switch on its own.
03Nothing leaves the buildingIP-sensitive teams will not send RTL to a cloud service. Local-first is the precondition for the conversation.
04Tool sprawl is the hidden costEvery additional vendor is another format, another script, another support path. Consolidation was valued independently of price.
What this does and does not prove

This validates the infrastructure thesis - determinism, licensing, locality, consolidation. It does not yet validate our physical-design and reliability roadmap. That is precisely what the design-partner beta is scoped to test.

Market

A $34.4B market, and the fastest-growing line in it is ours

Segment2024CAGR2030
EDA software$15.4B9.4%$26.5B
Semiconductor IP$8.2B9.5%$14.2B
Custom chip design$5.9B10.6%$10.8B
AI chip design acceleration$1.8B38.0%$13.3B
Total addressable$34.4B12.3%$69B
$12.1BServiceable marketThe secondary tool tier plus AI-accelerated design - the part we can sell into without displacing a core signoff engine.
500–800Teams we can reachGlobal fabless startups, IP vendors and design service houses running full custom flows, plus 130+ DPIIT semiconductor startups in India.

Core signoff is a fortress - decades of foundry certification and customer trust sit behind it. The tier next to it carries most of the tool count and a large share of the licence spend, with none of that certification lock-in. That is the part a new entrant can actually take, and the part nobody has made AI-native.

What is next

The next eighteen months

Month 3Escanor beta deployed on design-partner hardware
Month 6CDCBit wedge live with the first paying teams
Month 9–12ML layer live across the priority tools
Month 18Full suite plus AI layer, fifteen to twenty tools contracted
In person

Engineer-led, not booth-led

September 2026DVCon India · Bengaluru
September 2026SEMICON India · Delhi

Any engineer should be able to go from idea to silicon without a $500,000 licence standing in the way.

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