Loading page
The Toolset
Five stages cover the journey from spec to GDSII to 3D-IC - with analog and RF ahead. Live tools ship deep; everything else is labeled honestly.
Counts reflect the public tool registry; in-development tools are labeled as such.
01From intent to RTL
Turn specs and architecture decisions into clean, reviewable RTL - register maps, interconnect, memory, and clocking included.
One register spec, every output - RTL, UVM RAL, C headers, and documentation that never drift apart.
Explore RegBit →In development · names only until they ship - honest status, always
02From RTL quality to functional closure
Catch issues the moment they exist: static signoff on the RTL itself, then simulation, testbenches, assertions, coverage, and debug in one loop.
Catch RTL issues before they reach signoff - deep SystemVerilog linting in your editor and your CI.
Explore LintBit →Author and visualize UPF power intent - see your power domains instead of hand-writing brittle files.
Explore VisUPF →Lint, merge, and formally prove your timing constraints - and draft them from natural language.
Explore VisSDC →A waveform viewer that understands your design - protocol decoding and AI-assisted debug, at desktop speed.
Explore WaveBit →In development · names only until they ship - honest status, always
03From netlist to routed silicon
Synthesis, floorplanning, power delivery, place-and-route, static timing, extraction, and ECO - the physical flow as one connected cockpit.
A modern RTL synthesis suite - clean C++ core, built to be scripted, inspected, and trusted.
Explore Stella →A static timing engine with a real Python API - timing analysis you can script, query, and automate.
Explore SAC →In development · names only until they ship - honest status, always
04From analysis to tapeout confidence
Power integrity, electromigration, thermal, DRC, LVS, ERC and final GDS checks - the last mile before silicon, without the last-mile chaos.
In development · names only until they ship - honest status, always
05Beyond the single die
3D-IC and advanced packaging today; analog and RF design flows next. The platform grows in every direction chips do.
In development · names only until they ship - honest status, always
✦ The layer above the stages
Cross-cutting infrastructure that turns fifty tools into one platform: local-first orchestration, reproducible flows, and a managed PDK substrate. This is what makes the suite a suite.
Orchestrate your entire EDA flow as a graph - reproducible runs, convergence loops, and full visibility.
Explore FlowBit →The PDK substrate - immutable, content-addressed process kits with lockfiles, so every run is reproducible.
Explore Silicrate →See the live tools on your own designs, or run everything locally with Escanor.